The present invention relates to a semiconductor device functioning as a field effect transistor including a heterojunction and a method for fabricating the same.
Radio frequency (RF) semiconductor devices have heretofore been fabricated using a substrate made of a compound semiconductor like GaAs. Recently, however, technology of fabricating RF semiconductor devices using a novel mixed crystal semiconductor, which is much more compatible with a silicon process, has been researched and developed. Among other compounds, silicon germanium, which is expressed by a chemical formula Si1xe2x88x92xGex (where x is a mole fraction of Ge), is highly compatible with a silicon process in view of the fabrication technology applicable thereto. Thus, if Si1xe2x88x92xGex is used, then it is possible to take full advantage of richly cultivated silicon processing technology. In addition, SiGe and silicon (Si) together form a heterojunction therebetween. Thus, by utilizing the variability of its composition Si1xe2x88x92xGex (where 0 less than x less than 1) and the strain caused around the heterojunction, any device can be designed freely. Furthermore, carriers can move at a higher mobility in an SiGe layer than in an Si layer. Accordingly, a semiconductor device including an SiGe layer can operate faster with reduced noise. Paying special attention to the advantages of SiGe such as these, bipolar transistors and field effect transistors with an Si/SiGe heterojunction have been proposed, modeled and used practically.
For example, Solomon et al. of IBM Corp. proposed a heterojunction MOS transistor (HMOS transistor) including an Sixe2x80x94Ge layer as disclosed in Japanese Laid-Open Publication No. 3-3366. In this specification, the HMOS transistor of Solomon et al. will be labeled as first prior art example for convenience sake.
FIG. 13(a) is a cross-sectional view illustrating a structure of such an HMOS transistor according to the first prior art example. FIG. 13(b) is a cross-sectional view illustrating the region R50a shown in FIG. 13(a). FIG. 13(c) is a cross-sectional view illustrating movement, diffusion and segregation of Ge atoms after the HMOS transistor of the first prior art example, including a thin Si cap layer, has been annealed. And FIG. 13(d) is a cross-sectional view illustrating movement, diffusion and segregation of Ge atoms after the HMOS transistor of the first prior art example, including a thick Si cap layer, has been annealed. Only the region R50b shown in FIG. 13(b) is illustrated in FIGS. 13(c) and 13(d).
As shown in FIG. 13(a), the HMOS transistor includes: Si substrate 501; p+-type polysilicon gate electrode 516; SiO2 layer 517; intrinsic (i-) Si1xe2x88x92yGey layer 519 (where y is a mole fraction of Ge); i-Si cap layer 542; source contact 551 connected to a source region 553; and drain contact 552 connected to a drain region 554. In FIG. 13(a), the SiO2/Si and Si/Si1xe2x88x92yGey interfaces are identified by the reference numerals 535 and 536, respectively.
The HMOS transistor shown in FIGS. 13(a) through 13(c) is a p-channel MOS transistor. The source/drain regions 553 and 554 and the gate electrode 516 thereof are in similar shapes to those of an ordinary Si MOS transistor. But the p-channel is formed within Si1xe2x88x92yGey layer 519 to further increase the conductivity thereof. The atomic radius of Ge atoms 506 is greater than that of Si atoms. Thus, the i-Si1xe2x88x92yGey layer 519 receives a compressive strain because there is a lattice misfit between the i-Si1xe2x88x92yGey layer 519 and the Si substrate 501. Generally speaking, a phenomenon relaxing compressive strain is likely to occur during an epitaxy. Thus, it is not easy to stack the Si and SiGe layers consecutively while maintaining the crystallinity thereof. However, if the i-Si1xe2x88x92yGey layer 519 is deposited to a critical thickness thereof or less, then no dislocations, which ordinarily relax the strain, are brought about near the Si/Si1xe2x88x92yGey interface 536. As a result, these layers 519 and 542 can be stacked one upon the other in an equilibrium state with the crystallinity thereof maintained. In general, strain changes a band structure and the carrier mobility of holes. In an Si/Si1xe2x88x92yGey heterojunction device, however, if the Ge mole fraction y is adjusted within such a range as not causing the dislocations, then the band offset around the interface can be optimized thanks to the compressive strain and the mobility of holes can be increased. That is to say, as shown in FIG. 13(b), the holes can be confined in a heterobarrier by utilizing the offset at the valence band in the Si/Si1xe2x88x92yGey heterojunction device. Accordingly, the Si/Si1xe2x88x92yGey heterojunction device is applicable as a heterojunction PMOSFET. When a negative voltage is applied to the gate electrode 516, the polarity of the regions surrounding the Si/Si1xe2x88x92yGey interface 536 is inverted, thus forming a p-channel, where positive carriers (holes) are confined, along the Si/Si1xe2x88x92yGey interface 536. As a result, those carriers travel at a high velocity from the source region 553 toward the drain region 554. In this case, if the Si/Si1xe2x88x92yGey interface 536 is planar, then the p-channel is formed along the planar Si/Si1xe2x88x92yGey interface 536, and therefore, the carriers can move at an even higher velocity.
As can be seen, a field effect transistor using SiGe can operate faster than a field effect transistor using Si.
Ismail proposed a heterojunction CMOS transistor in 1995 IEEE IEDEM Tech. Dig. 509 (see also M. A. Armstrong, D. A. Antoniadis, A. Sadek, K. Ismail and F. Stern, 1995 IEEE IEDEM Tech. Dig. 761 and Japanese Laid-Open Publication No. 7-321222). In this specification, this HCMOS transistor will be labeled as second prior art example for convenience sake.
FIG. 14(a) is a cross-sectional view illustrating a semiconductor device according to the second prior art example. FIG. 14(b) illustrates a vertical cross section of a region including gate electrode, gate insulating film and channel in the PMOS 530 or NMOS transistor 531 shown in FIG. 14(a). On the left-hand side of FIG. 14(b), shown is a valence band corresponding to a negative gate bias voltage applied. On the right-hand side of FIG. 14(b), shown is a conduction band corresponding to a positive gate bias voltage applied. FIG. 14(c) is a cross-sectional view of the region R60b shown in FIG. 14(b) illustrating movement and segregation of Ge atoms after the HCMOS transistor of the second prior art example has been annealed. As shown in FIG. 14(a), the HCMOS transistor includes Si substrate 501, PMOSFET 530, NMOSFET 531, n-well 532 and shallow trench isolation (STI) region 534. As shown in FIG. 14(b), Si1xe2x88x92xGex buffer layer 523, i-Si1xe2x88x92xGex spacer layer 521, xcex4-doped layer 522, i-Si layer 520, i-Si1xe2x88x92yGey layer 519, i-Si layer 518, SiO2 layer 517 and polysilicon gate electrode 516 are stacked in this order. In FIG. 14(b), first, second and third interfaces are identified by the reference numerals 537, 538 and 539, respectively.
In the example illustrated in FIG. 14(a), an HCMOS device is made up of n- and p-channel field effect transistors each including the Si1xe2x88x92yGey layer 519. According to this prior art example, superior conductivity is attainable compared to a homojunction transistor formed on an Si substrate. In addition, since the n- and p-channel MOS transistors are formed using a common multilayer structure, the fabrication process thereof is simpler.
As shown in FIG. 14(b), strain can be relaxed by the Si1xe2x88x92xGex buffer layer 523, on which the i-Si1xe2x88x92xGex (where x=0.3) spacer layer 521 is formed. The xcex4-doped layer 522 for supplying carriers to the n-channel is defined within the i-Si1xe2x88x92xGex spacer layer 521. The i-Si layer 520 to which a tensile strain is applied, the i-Si1xe2x88x92yGey layer 519 of which the strain has been relaxed, and the i-Si cap layer 518 to which a tensile strain is applied, are stacked one upon the other on the i-Si1xe2x88x92xGex spacer layer 521. On the i-Si cap layer 518, the SiO2 layer 517 as the gate oxide film and the gate electrode 516 are formed in this order.
On the left-hand side of FIG. 14(b), shown is a valence band appearing when a negative gate bias voltage is applied to the multi-layered transistor shown in the center of FIG. 14(b) to make the transistor operate as PMOSFET. On the right-hand side of FIG. 14(b), shown is a conduction band appearing when a positive gate bias voltage is applied to the multi-layered transistor to make the transistor operate as NMOSFET. That is to say, one of the transistors can operate as PMOSFET and the other as NMOSFET by using the same multilayer structure.
To make the portion shown in the center of FIG. 14(b) operate as PMOSFET, holes are confined in the p-channel by utilizing the offset at the valence band in the first interface 537 between the i-Si1xe2x88x92yGey layer 519 and i-Si cap layer 518. And a negative gate bias voltage is applied to the gate electrode 516, thereby making the holes move. In this case, if the magnitude of the strain is adjusted by changing the Ge mole fraction y in the i-Si1xe2x88x92yGey layer 519, then the band offset in the first interface 537 is controllable. The conductivity of the holes in the i-Si1xe2x88x92yGey layer 519, to which the compressive strain is applied, is higher than that of the holes in the Si layer. Thus, excellent PMOS performance is attainable.
To make the portion shown in the center of FIG. 14(b) operate as NMOSFET, electrons are confined in the n-channel by utilizing the offset at the conduction band in the third interface 539 between the i-Si layer 520 and i-Si1xe2x88x92xGex spacer layer 521. And a positive gate bias voltage is applied to the gate electrode 516, thereby making the electrons move. Unlike the PMOSFET, the n-channel is formed within the Si layer 520. However, the i-Si layer 520 is receiving a tensile strain because there is a lattice misfit between the i-Si layer 520 and i-Si1xe2x88x92xGex spacer layer 521. Accordingly, the band degeneracy of the electrons has been eliminated and the conductivity of the electrons is higher than that of electrons located within a normal channel in the Si layer. In this case, if the magnitude of the strain is adjusted in the same way as the PMOSFET, then the band offset is also controllable.
As can be seen, in the semiconductor device according to the second prior art example where the Si/SiGe heterojunctions are formed, the same multilayer structure shown in the center of FIG. 14(b) can be selectively used as NMOSFET or PMOSFET by changing the direction of the gate bias voltage. Accordingly, an HCMOS device with excellent conductivity can be obtained through relatively simple process steps if a single multilayer structure is separated and isolated via the STI to define separate source/drain regions and gate electrode.
However, the devices according to the first and second prior art examples have the following drawbacks.
In the field effect transistors such as the MOSFET according to the first prior art example, carriers travel along the inversion region around the Si/Si1xe2x88x92yGey interface 536. Thus, the interface states greatly affect the mobility of the carriers, and the operating speed of the device. That is to say, to make the device operate at high speeds, the structure of the Si/Si1xe2x88x92yGey interface 536 should not be out of order, i.e., the interface thereof should be definitely defined and planar without any fluctuations or unevenness.
However, it is difficult for the device using the Si/Si1xe2x88x92yGey heterojunction to maintain the definitely defined, planar interface because of the following reasons.
For example, when the i-Si1xe2x88x92yGey layer 519 and i-Si cap layer 542 are stacked consecutively as shown in FIG. 13(b), then interdiffusion is caused between Si atoms (not shown) in the i-Si cap layer 542 and Ge atoms 506 in the i-Si1xe2x88x92yGey layer 519. As a result, the structure of the Si/Si1xe2x88x92yGey interface 536 becomes out of order and the boundary between the i-Si1xe2x88x92yGeylayer 519 and i-Si cap layer 542 cannot be located definitely anymore. In FIG. 13(b), the i-Si1xe2x88x92yGey layer 519 and i-Si cap layer 542 are illustrated as being clearly divided layers for the illustrative purposes only. Actually, though, the boundary between these layers 519 and 542, i.e., the interface 536, is not so definite as the illustrated one.
In a fabrication process of a semiconductor device such as a field effect transistor, just after dopants have been introduced by ion implantation, for example, to define p- and n-type doped regions, those dopants are not located at crystal lattice sites. Thus, to make these dopants act as donors or acceptors, annealing is conducted at an elevated temperature, thereby activating the dopants. In this case, annealing is carried out at a temperature as high as about 900xc2x0 C. Thus, the Ge atoms 506 in the i-Si1xe2x88x92yGey layer 519 move and diffuse particularly actively.
FIGS. 13(c) and 13(d) are cross-sectional views illustrating post-annealing states of the region R50b shown in FIG. 13(b) where the thicknesses of the i-Si cap layer 542 are relatively small and large, respectively. As a result of annealing, the Ge atoms 506 move and diffuse to cause segregation or lattice defects and the definiteness and planarity of the Si/Si1xe2x88x92yGey interface 536 are lost as disclosed by F. K. LeGoues, S. S. Iyer, K. N. Tu and S. L. Delage in Mat. Res. Soc. Symp. Proc., Vol. 103, 185 (1988). As also described in this document, the movement, diffusion and segregation of the Ge atoms are particularly noticeable in an SiGe layer to which some strain is applied.
According to the first and second prior art examples, the SiO2 layer 517 is formed as the gate oxide film by thermal oxidation. However, during the thermal oxidation, the Ge atoms are segregated at the Si/SiO2 interface 535 and increase the oxidation rate as disclosed by G. L. Patton, S. S. Iyer, S. L. Delage, E. Ganin and R. C. Mcintosh in Mat. Res. Soc. Symp. Proc., Vol. 102, 295 (1988). Such a phenomenon is believed to cause various adverse effects. For example, the interface level of the Si/SiO2 interface 535 rises, thus adversely affecting the mobility of carriers moving in the p-channel. The concentration distribution of Ge atoms might deviate from a desired one. And since the oxidation rate increases, it might become difficult to form a thin gate oxide film.
Thus, if the thickness of the i-Si cap layer 542 is set larger than the diffusion length of the Ge atoms as shown in FIG. 13(d), it might be possible to prevent the carrier mobility from being adversely affected by the structural disorder of the Si/Si1xe2x88x92yGey interface 536. In such a case, however, a potential difference is also applied to the i-Si cap layer 542. Accordingly, the driving power of the transistor might possibly decrease. Also, since a parasitic channel is formed near the Si/SiO2 interface 535 as shown in FIG. 13(d), the carriers might deviate from the intended path and the mobility thereof might decrease as a result. In addition, the structural disorder of the Si/Si1xe2x88x92yGey interface 536 and the lattice defects such as dislocations resulting from the annealing process are still left as they are.
Some countermeasures have been taken to solve such problems. For example, the annealing temperature could be lowered to a certain degree if the i-Si1xe2x88x92yGey layer 519 and i-Si cap layer 542 are grown epitaxially after the dopant ions have been implanted into the Si substrate 501 to define source/drain regions and then activated through annealing. In such a case, however, the ion-implanted regions and the gate electrode 516 cannot be self-aligned with each other, thus increasing the number of process steps. In addition, the dopant profile and gate alignment accuracy deteriorates due to the mask-to-mask placement error involved with a photolithographic process.
The drawbacks of the first prior art example have been specified above. It is clear that the same statement is true of the second prior art example, because structural disorder is also brought about in the first and second Si/Si1xe2x88x92yGey interfaces 537, 538 and in the third Si/Si1xe2x88x92xGex interface 539.
An object of the present invention is providing a semiconductor device including an Si/SiGe heterojunction, for example, with its thermal budget increased by enhancing the interfacial structure, or by getting the definiteness and planarity thereof maintained even if annealing is conducted thereon, and a method for fabricating such a device.
A semiconductor device according to the present invention includes: a semiconductor substrate; a first semiconductor layer, which is formed within the semiconductor substrate and is made of mixed crystals of multiple elements; and a second semiconductor layer, which is formed within the semiconductor substrate to be in contact with the first semiconductor layer and contains an inhibitor for suppressing movement of at least one of the constituent elements of the first semiconductor layer. The semiconductor device functions as a device using a heterojunction formed between the first and second semiconductor layers.
In the inventive semiconductor device, the movement of mixed crystal element through the interface between the first and second semiconductor layer can be suppressed. Thus, even after annealing has been carried out, the quality of the mixed crystals can be kept good, the structural disorder of the interface between the first and second semiconductor layers can be suppressed and the interface can be kept relatively definite and planar. That is to say, the mobility of the carriers moving along the interface can be kept high, thus obtaining a semiconductor device with an increased thermal budget.
In one embodiment of the present invention, where the first and second semiconductor layers are made of Si1xe2x88x92yGey (where 0 less than y less than 1) and Si, respectively, the inhibitor is preferably C (carbon).
In this particular embodiment, the concentration of C is preferably 1% or less to keep the band structure of the Si layer appropriate.
In an embodiment where the Si layer is located closer to the surface of the semiconductor substrate than the Si1xe2x88x92yGey layer is, a concentration of C in the Si layer preferably has such a profile as decreasing from the Si1xe2x88x92yGey layer toward the surface of the semiconductor substrate. In such a case, it is possible to suppress C from being diffused or segregated around the surface of the semiconductor substrate. Thus, decline in reliability, which usually results from the mixture of C into the gate insulating film, is avoidable effectively.
In another embodiment, the Si1xe2x88x92yGey layer may have a thickness equal to or smaller than its critical thickness, and receive a compressive strain. In such an embodiment, the mobility of carriers moving through the channel can be further increased. At the same time, the movement of Ge atoms, which is usually brought about with a strain applied, can still be suppressed through this action.
In still another embodiment, the semiconductor device of the present invention may be a field effect transistor further including: a gate electrode formed on the semiconductor substrate; and a channel formed in the Si layer under the gate electrode.
In this particular embodiment, the device may further include a gate insulating film interposed between the gate electrode and the Si layer.
More particularly, the device may further include an intrinsic Si layer interposed between the Si layer and the gate insulating film.
In still another embodiment, the Si layer may be located closer to the surface of the semiconductor substrate than the Si1xe2x88x92yGey layer is. In such an embodiment, the device may further include: a second Si layer, which is formed under the Si1xe2x88x92yGey layer and contains C; an Si1xe2x88x92xGex layer formed under the second Si layer, where 0 less than x less than 1; and a xcex4-doped layer, which is formed within the Si1xe2x88x92xGex layer in a region closer to the second Si layer and contains a high-concentration carrier dopant. In this particular embodiment, the semiconductor device of the present invention is implementable as a CMOS device including p- and n-channel field effect transistors. The p-channel field effect transistor includes a gate electrode and a p-channel. The gate electrode is formed on the semiconductor substrate, while the p-channel is defined in the Si1xe2x88x92xGex layer under the gate electrode. The n-channel field effect transistor includes a gate electrode and an n-channel. The gate electrode is also formed on the semiconductor substrate, while the n-channel is formed in the Si layer under the gate electrode.
That is to say, the same multilayer structure can be used as active region for both the n- and p-channel field effect transistors. Thus, a CMOS device including a heterojunction can be fabricated with the number of process steps reduced.
In this particular embodiment, the Si and second Si layers preferably receive a tensile strain, while a strain applied to the Si1xe2x88x92xGex layer has preferably been relaxed.
As an alternative, the device may further include gate insulating films formed between the gate electrodes of the p- and n-channel field effect transistors and the Si layer, respectively. In such an embodiment, a concentration of C in the Si layer preferably has such a profile as decreasing from the Si1xe2x88x92xGex layer toward the surface of the semiconductor substrate.
In still another embodiment, a concentration of C in the second Si layer preferably has such a profile as decreasing from the Si1xe2x88x92xGex layer toward the Si1xe2x88x92yGey layer. In such a case, a change of band structure in accordance with the concentration variation of C can be taken advantage of. As a result, only the threshold voltage of the n-channel field effect transistor can be regulated at an appropriate value without affecting the characteristics of the p-channel field effect transistor at all.
In another alternate embodiment, a content of Ge in the Si1xe2x88x92yGey layer may increase from the second Si layer toward the Si layer. In such an embodiment, only the threshold voltage of the p-channel field effect transistor can be regulated at an appropriate value without affecting the characteristics of the n-channel field effect transistor at all.
A first exemplary method for fabricating a semiconductor device according to the present invention includes the steps of: a) forming a first semiconductor layer, which is made of mixed crystals of multiple elements, on a substrate; b) forming a second semiconductor layer on the first semiconductor layer; and c) doping the first and second semiconductor layers with an inhibitor by implanting ions of the inhibitor thereto. The inhibitor suppresses movement of at least one of the constituent elements of the first semiconductor layer. The step c) is performed after the step b) has been performed. The semiconductor device functions as a device using a heterojunction formed between the first and second semiconductor layers.
According to this method, even if the device is subsequently annealed, the movement of mixed crystal elements is still suppressible. Accordingly, the structural disorder of the interface between the first and second semiconductor layers can be relieved, thus increasing the mobility of carriers moving through the channel of the semiconductor device.
In one embodiment where the first and second semiconductor layers are made of Si1xe2x88x92yGey (where 0 less than y less than 1) and Si, respectively, the inhibitor is preferably C.
In this particular embodiment, the method may further include the steps of: forming an intrinsic Si layer on the Si layer after the step b) has been performed and before the step c) is performed; and forming an oxide film substantially reaching the Si layer by oxidizing the intrinsic Si layer after the step c) has been performed. In this manner, the oxide film can be formed as the gate insulating film while suppressing the movement of Ge atoms in the Si1xe2x88x92yGey layer.
A second exemplary method for fabricating a semiconductor device includes the steps of: a) forming a first semiconductor layer, which is made of mixed crystals of multiple elements, on a substrate; and b) forming a second semiconductor layer, which contains an inhibitor, on the first semiconductor layer such that the concentration of the inhibitor in the second semiconductor layer decreases upward. The inhibitor suppresses movement of at least one of the constituent elements of the first semiconductor layer. The semiconductor device functions as a device using a heterojunction formed between the first and second semiconductor layers.
According to this method, the structural disorder of the interface between the first and second semiconductor layers can be suppressed, while preventing the reliability of the semiconductor device from declining due to the diffusion of the inhibitor toward the surface of the substrate.
In one embodiment of the present invention, CVD, UHV-CVD or MBE process may be performed in the step b).